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Revision 0.6
OMAP TM 4 PandaBoard System
Reference Manual
November 29, 2010
DOC-21010
2.4
TWL6030 Power Companion IC
The TWL6030 device is a small (7 x 7 mm, 0.4mm pitch) 256 ball FBGA that provides many functions
used on the Platform. Shown below is a feature list of the major functions/interfaces provided by the
TWL6030 device that are utilized on the Panda platform. This list below doesn’t include all device
functionality, just that which is used on the PandaBoard.
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A power management system (FSM)
1 HS-I2C interface ( ≤ 2.4Mbits/s) for all Phoenix Power IC GP control commands (CTL-I2C)
1 HS-I2C interface ( ≤ 2.4Mbits/s) for all Smart-Reflex Class 3 control commands (SR-I2C)
MMC card detection mechanism
A 24MHz RC oscillator
A 32kHz RC oscillator for a fast device start-up
A high-performance crystal oscillator, for 32.768kHz external crystal
A Real Time Clock (RTC) resource
Power supply resources:
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11 Low Drop Out (LDO) regulators
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1 for internal purposes only (VRTC)
1 for internal and platform needs (VANA)
9 for platform needs (VAUX1, VAUX2, VAUX3, VCXIO, VDAC, VMMC,
VPP, VUSB, VUSIM)
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7 buck SMPS with:
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DVS capability Smart-Reflex Class 3 compatible (VCORE1, VCORE2,
VCORE3)
1 for I/O supply (V1V8), with specific PWMFORCE input control
1 for LDOs pre-regulation (V2V1) and Phoenix Audio features
1 for memory supply (VMEM)
1 for external modem, RF transceiver or I/Os (V1V29)
? 3 general-purpose enables for possible platform upgrades (REGEN1, REGEN2, SYSEN)
2.4.1
TWL6030 Core SMPS Outputs
The TWL6030 implements three Switch Mode Power Supplies (SMPS) that source the three main core
voltage rails for the OMAP4430 processor. The default voltage of all of these supplies is 0.95V, and each
should be adjusted as required by S/W for the desired processor OPP.
VCORE1 is a 1200mA SMPS that is used to power the VDD_MPU balls on the OMAP4430 processor
(net name VDD_VCORE1, 9 balls total). VCORE2 is a 600mA SMPS that is used to power the
VDD_IVA_AUDIO balls on the processor (net name VDD_VCORE2, 10 balls total). VCORE3 is a
600mA SMPS that is used to power the VDD_CORE balls on the processor (net name VDD_VCORE3,
34 balls total) and the VDDA_DLLn_LPDDR21 and VDDA_DLLn_LPDDR22, where n=0 and 1 (4 balls
total).
Page 18 of 82
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